It is known to use buffers to temporarily store information from a data stream pending output of that data stream to its ultimate destination. The use of the buffer enables bursts in volume of a data stream to be accommodated where there is a limited capacity for routing data from a data stream generator to a data stream receptor. For example, there may be a bus of limited bandwidth or a fixed number of data pins providing a maximum possible data transfer capacity.
Buffering of data streams is frequently implemented in tracing systems, where buffering of trace data streams is performed. It is known to use a trace buffer to reduce the number of trace pins required by smoothing out bursts in incoming trace data so that only enough trace pins to support an average trace bandwidth are required, rather than sufficient trace pins to support a peak in the output of the trace data source. However, in implementing buffers such as trace buffers there is a problem to determine how big the capacity of the buffering circuitry needs to be to suit a particular data processing situation.
Buffer capacity estimation is typically done by performing a number of different test runs in test systems implemented on, for example, Field Programmable Gate Arrays (FPGAs) using a number of different fixed buffer sizes and seeing what happens in terms of system performance in view of the different buffer sizes. However, the process of determining an appropriate buffer size in this way is time consuming and inefficient, and cannot be used when a data processing system has been fabricated on real silicon where the buffer memory will typically be implemented as a fixed size random access memory (RAM).
Accordingly, there is a requirement for providing more efficient buffering of data streams that is adaptable to the diverse buffering requirements of different data processing tasks.